A TCP (tape carrier package), a COF (chip on film), and the like are examples of a semiconductor device having a structure in which a semiconductor element is connected to and mounted on a flexible substrate. The TCP and the COF have the following distinctions, for example.
First, the TCP has an opening section which is provided in advance to cause the semiconductor element to be mounted on an insulation tape. A wiring pattern is formed so that wires of the pattern reach out so that leading ends of the wires are bonded to the semiconductor element. On the other hand, the COF differs from the TCP in that the COF has no opening section for mounting the semiconductor element, and the semiconductor element is connected to and mounted on a wiring pattern formed on a surface of a thin film insulation tape.
In the TCP, a thickness of the wiring pattern is 18 μm or greater because the wires of the wiring pattern reach out from the TCP. As such, it is difficult to form a wiring pattern having a pitch of below 45 μm. On the other hand, the COF allows the wiring pattern to have a thickness of 8 μm or less because the wiring pattern is formed on the surface of the thin film insulation tape. Thus, the wiring pattern is easily formed so as to have a wiring pitch of 35 μm or less in the COF. In this regard, the COF differs from the TCP.
Further, the TCP has a slit in a portion to be folded after the TCP is mounted onto a liquid crystal panel or the like. In this regard, unlike the TCP, the COF has no slit via which the folding is carried out, so that the COF can be flexibly folded over any portion of the thin film insulation tape.
The TCP is formed by stacking copper foil on the insulation tape made of polyimide using bonding adhesive. On the other hand, the COF is different from the TCP in that the COF is formed using either of a casting method or a spattering method (metallizing method). In the casting method, a backside of the copper foil is coated with polyimide or the like and then hardened. In the spattering method, copper is spattered and stacked on a thin film insulating layer, which is made of polyimide or the like.
For its intended use, the COF employs a thin film insulation tape which can be freely folded. Further, wires of the wiring pattern disposed on a surface of the thin film insulation tape are electrically connected to corresponding terminals of the semiconductor element, respectively, while a connector section for external connection is connected to a liquid crystal panel, a printed board, or the like. A solder resist is applied to other exposed portions of the wiring pattern. This allows the wiring pattern to be securely insulated.
As described above, the COF is a technique which facilitates fine pitch design of the wiring pattern. However, the COF actually employs a wiring pattern having a thickness of 8 μm to 18 μm according to a wiring pitch of the wiring pattern, i.e., 35 μm to 50 μm or greater. In this regard, no patent document describes such a technique related to the thickness of the wiring pattern. On the other hand, as to the TCP, a technique related to the thickness of the wiring pattern is described in patent reference 1, for example.
With reference to FIGS. 11 and 12, a conventional COF is described. FIG. 11 is a cross-sectional view illustrating a schematic structure of a conventional COF 101. FIG. 12 is a cross-sectional view illustrating a schematic structure of the COF 101 taken along line C-C′ of FIG. 11. As illustrated in FIGS. 11 and 12, the COF 101 has a structure in which a semiconductor element 102 is connected to and mounted on a tape carrier 103.
In the tape carrier 103 of the COF 101 illustrated in FIGS. 11 and 12, a wiring pattern 105 is formed on an insulation tape 104. The wiring pattern 105 is realized by forming copper foil or spattered copper having a thickness of 8 μm to 18 μm, using the casting method or the spattering method (metallizing method). As illustrated in FIGS. 11 and 12, the wiring pattern 105 is formed so as to have a uniform thickness in all regions including a region where the semiconductor element 102 is connected to and mounted on and other regions.
[Patent Reference 1]
Japanese Unexamined Patent Publication, No. 32227/1998 (Tokukaihei 1998-32227, publication date: Feb. 3, 1998)
According to the Patent Reference 1, a thickness of a wiring pattern is made thicker (26 μm) in an opening section for mounting a semiconductor element and in a slit section via which the folding is carried out. This allows an improvement in mechanical strength of wiring pattern. On the other hand, the thickness of the wiring pattern is made thinner (18 μm) in an OLB (outer lead bonding) section, to which a liquid crystal panel or a substrate is connected. This allows top portions of the wiring pattern to be broad in width to secure a bonding area.
However, the wiring pattern in the opening section, where the semiconductor element is mounted, has actually the finest pitch. As such, it is necessary to make thinner the thickness of the wiring pattern. Even if the wiring pattern is formed so as to have a uniform thickness of 18 μm in all regions, mechanical strength will not be affected. Actually, mass-produced TCP semiconductor devices employ wiring patterns having a thickness of 18 μm. That is, a technique disclosed in patent reference 1 is neither realistic nor necessary. As described here, it is difficult to realize in the actual TCP such a fine pitch of the wiring pattern.
Compared to the TCP, the COF facilitates the realization of such a fine pitch of the wiring pattern (inner lead). With regard to wiring patterns (inner lead) in mass-produced semiconductor devices, the TCP has a limit wiring pitch of 45 μm, whereas the COF realizes a wiring pitch of 35 μm. Further, it is believed that a wiring pitch of 30 μm or less is also possible.
Notwithstanding, according to the reviews and considerations of an inventor of the present application, the inventor encountered the following problems when realizing the fine pitch in the COF.
For example, one of the above problems is that, when realizing a fine pitch of a wiring pattern (inner lead), it becomes difficult to carry out a pattern etching with respect to the wiring pattern (inner lead) so that the wiring pattern has a good shape while the wiring pattern has a conventional thickness of 8 μm. This is especially the case when the wiring pitch becomes 30 μm or less.
That is, as the wiring pattern (inner lead) has a finer pitch, a width of the wiring pattern (inner lead) also needs to be smaller. This makes it difficult that the wiring pattern is etched so as to have a good trapezoid cross section. This causes the cross section of the wiring pattern to become close to a triangle shape, and causes the thickness of the wiring pattern (inner lead) to have a greater variation.
In this regard, the following describes in more detail with reference to FIG. 13.
FIG. 13 illustrates a structure obtained by making finer the pitch of the wiring pattern 105 in the conventional COF 101 illustrated in FIGS. 11 and 12. For example, a wiring pitch of greater than 35 μm does not affect etching applied to the wiring pattern 105. However, with a wiring pitch of less than 35 μm, it becomes difficult to carry out an etching process to have a trapezoid cross section which indicates a good cross sectional shape of the wiring pattern 105. Under such a condition, cross section of the wiring pattern 105 becomes closer to a triangle shape as illustrated in FIG. 13. Further, after the etching process, the thickness of the wiring pattern 105 has a greater variation, which appears to degrade bonding between the semiconductor element 102 and the wiring pattern 105.
As a solution for the above problems, it may be contrived to reduce the thickness of the copper foil or spattered copper (wiring pattern). By reducing the thickness of the copper foil or spattered copper (wiring pattern), it becomes possible to carry out the pattern etching so that the wiring pattern has a good shape. For example, even when the wiring pattern (inner lead) has a wiring pitch of 30 μm, it is possible to carry out the pattern etching with respect to the wiring pattern to have a trapezoid cross section which indicates a good cross sectional shape of the wiring pattern, by reducing the thickness of the copper foil or spattered copper (wiring pattern) to be approximately 5 μm.
However, the reduction in thickness of the wiring pattern (inner lead), caused by realization of fine pitch of the wiring pattern, gives rise to the problem of degrading the mechanical strength of the wiring pattern. This may cause the wiring pattern to be broken or exfoliated during a period from a step for connecting and mounting a semiconductor element to a step for mounting a module of a COF semiconductor device.
In this regard, the following describes in more detail, with reference to FIGS. 14 and 15. FIG. 14 illustrates a structure obtained by making thinner the thickness of the copper foil or spattered copper forming the wiring pattern 105 in the conventional COF 101 illustrated in FIGS. 11 and 12. FIG. 15 is a cross-sectional view illustrating a schematic structure of the COF 101 taken along line D-D′ of FIG. 14. As illustrated in FIGS. 14 and 15, it is possible to carry out a etching process to the wiring pattern to have a good cross sectional shape, by reducing the thickness of the copper foil or spattered copper. However, due to the degrading of its mechanical strength, the wiring pattern may tend to be broken or exfoliated during a period from the step for connecting and mounting a semiconductor element to the step for mounting a module of a COF semiconductor device.
Currently, there has been a demand on multi-pin support for the COF. Further, reduction in size and thickness of the COF have been also demanded. These demands will be met by realizing (i) fine pitch of the connecting sections for connecting the semiconductor element and the external connection connector section where the wiring pattern is connected, and (ii) reduction in thickness of the wiring pattern or the like. For this purpose, the width and thickness of the wiring pattern (inner lead) also needs to be reduced. However, the conventional techniques do not easily enable realization of fine pitch design as described above, because the COF needs to be flexibly folded while requiring improved mechanical strength which allows reduction in thickness of the wiring pattern.